/**************************************************************************** * wb_dma_3.pss * * Copyright 2023 Matthew Ballance and Contributors * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * Created on: * Author: ****************************************************************************/ import addr_reg_pkg::*; buffer MemBuf { rand bit[32] size; // Size of the data addr_handle_t addr_h; } resource Channel { } component WbDma { pool MemBuf mem_buf_p; bind mem_buf_p *; pool [16] Channel channels_p; bind channels_p *; action Mem2Mem { input MemBuf src_i; input MemBuf dst_o; rand addr_claim_s<> dst_claim; lock Channel channel; // Input and output size must be the same constraint dst_o.size == src_i.size; // DMA only transfers words constraint (dst_o.size % 4) == 0; // Specify size/alignment for allocation constraint dst_claim.size == dst_o.size; constraint dst_claim.alignment == 4; exec post_solve { dst_o.addr_h = make_handle_from_claim(dst_claim); } } action Mem2Dev { // TODO: fill in later } action Dev2Mem { // TODO: fill in later } } component pss_top { transparent_addr_space_c<> aspace; WbDma dma; exec init_down { transparent_addr_region_s<> region; region.addr = 0x8000_0000; region.size = 0x1000_0000; aspace.add_region(region); region.addr = 0x0000_0000; region.size = 0x1000_0000; aspace.add_region(region); } }