Posts — page 3
Working with Analysis Ports
For the most part, UVM and SystemVerilog make interactions with a dynamically-typed language surprisingly easy. There are a few exceptions where the developer of the SystemVerilog UVM code must step in to enable access to certain testbench elements. Analysis …
Accessing User-Defined SV Data from Python
We've seen how the [PyHDL-IF](http://github.com/fvutils/pyhdl-if) library makes it simple to implement UVM sequences and components in Python, and how Python can call back into SystemVerilog. But, a significant part of a testbench deals with user-defined data…
The Mechanics of UVM/Python Cross-Calling
It's not necessary to understand very much about how PyHDL-IF implements the bridge between Python and UVM, but useful to understand a bit. Doing so helps to understand what this library is and is not intended to do, and how you can best use it in your verifi…
Unlocking the Combined Strength of UVM and Python
UVM and Python are often positioned as rivals when it comes to their role in functional verification, with teams picking one or the other as the basis for a verification environments. Each have strengths, though, and using them together produces much strong…
Zuspec: Pythonic Model-Driven Hardware Development
Designing and implementing hardware is challenging, and is getting more difficult each year as systems become more complex. Design and verification teams are looking to boost productivity as a way to keep pace, while also looking for ways to provide models …
AI: Instigating a Developer Docs Renaissance?
There's been lots of discussion about the future of writing in the AI age. LLMs have shown their potential as a tool by helping authors of many genres brainstorm ideas, rough out content, and more. But, this automation comes with questions attached. If writin…
Re-Evaluating EDA DSLs: Becoming the Compiler
A key benefit of full languages is having full control over processing the language: being the compiler. Having full control over language processing is exactly what enables us target simulation and FPGA bitstream with the same SystemVerilog source simply by …
Re-Evaluating EDA DSLs in the AI Era
I've been looking for a new hardware-centric design language for the last couple of years. Or, more precisely, I've been looking for a hardware-centric design language that would allow me to realize my ideal silicon design flow. - Must support using the same…
PSS: Getting Outside the Box
In the [last post](https://bitsbytesgates.com/pss/2025/02/04/TranspilationandPSS.html), we showed a SystemVerilog implementation of a PSS model that printed "Hello World!". Interesting, perhaps, but quite a ways from being useful. In order to be useful, our …
Transpilation and PSS
You're probably familiar with compilers. They take a high-level input description -- typically a programming language -- and distill it down to an efficient low-level implementation. Typically the implementation is machine code or bytecode. In other words, …